Compression-free Checksum-based Fault-Detection Schemes for Pipelined Processors

Conference: ARCS 2007 - 20th International Conference on Architecture of Computing Systems 2007
03/15/2007 at Zurich, Switzerland

Proceedings: ARCS 2007

Pages: 6Language: englishTyp: PDF

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Fechner, Bernhard; Keller, Jörg (FernUniversität in Hagen, Fakultät für Mathematik und Informatik, 58084 Hagen, Germany)

We propose a fault-detection scheme for pipelined, multithreaded processors. The scheme is based on checksums and improves on previous schemes in terms of fault coverage and detection latency by not using compression but storing complete checksums from several pipeline stages. We validate the scheme experimentally and derive checksum polynomials that lead to perfect fault coverage.