Efficient Mapping and Functional Verification of Parallel Algorithms on a Multi-Context Reconfigurable Architecture
Conference: ARCS 2007 - 20th International Conference on Architecture of Computing Systems 2007
03/15/2007 at Zurich, Switzerland
Proceedings: ARCS 2007
Pages: 10Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Rullmann, Markus; Siegel, Sebastian; Merker, Renate (Dresden University of Technology, Dresden, Germany)
Filho, Julio A. Oliveira; Schweizer, Thomas; Oppold, Tobias; Rosenstiel, Wolfgang (University of Tübingen, Tübingen, Germany)
Parallel multi-context reconfigurable architectures provide very attractive platforms with respect to computational performance and reconfigurable features. Today’s challenge is the exploitation of this reconfigurable and computational potential to ascertain efficient solution for mapping applications onto these architectures. The demand for appropriate tools is evident. In this paper we provide a combination and a mutual adaption of two separate tools to create a continuous design flow for parallel multi-context reconfigurable architectures. Especially we present the interaction of a parameterized mapping tool for mapping compute intensive algorithms on processor arrays and a subsequent verification of the mapping results using the Configurable Reconfigurable Core (CRC) architecture model. The SystemC implementation of the CRC model leads to a cycle accurate functional simulation of the realization. Using this continuous design flow we derive an efficient realization of the edge detection algorithm (EDA) on a parallel multi-context reconfigurable architecture. We describe in detail how the parallel realization of the EDA has to be translated in a specification for programming the CRC model.