Scheduling and Communication-Aware Mapping of HW/SW Modules for Dynamically and Partially Reconfigurable SoC Architectures

Abstract:
In this paper, we present an approach for simultaneous scheduling and placement of communicating modules for SoC architectures including devices with partial reconfiguration support and at least one CPU. This approach includes (a) a detailed modeling of the communication of modules and an optimization model for finding the best temporal and spatial placement of modules on either CPU or on the reconfigurable device including communication and reconfiguration time overheads, (b) a real SoC platform for slot-based module relocation and on-chip inter-module communication called Erlangen SlotMachine (ESM), and (c) real experimental data based on experiments on this machine. Existing approaches either neglect inter-module communication, are not able to solve the related problem, or do not provide real applications implemented on real platforms.