Accelerating Physical Verification Using STPRL: a Novel Language for Test Pattern Generation
Conference: EMLC 2007 - 23rd European Mask and Lithography Conference
01/22/2007 - 01/26/2007 at Grenoble, France
Proceedings: EMLC 2007
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Nouh, Ahmed (Mentor Consulting Department, 51 Beirut St., Heliopolis, Cairo 11341, Egypt)
In this work, test-patterns, test-cases and layout-patterns generations are widely investigated in the sense of turnaround time for creation and/or modification. STPRL, a novel behavioral modeling language for test-pattern creation, is being proposed. The turn-around time for both creation and modification is hugely reduced at no degradation in either accuracy or performance. Furthermore, STPRL provides considerable performance improvements in custom testpatterns creation over available automatic layout creation tools. Our method has been verified with real data at different node-technologies and for migration from and between different technology nodes.