Data Preparation for EBDW

Conference: EMLC 2007 - 23rd European Mask and Lithography Conference
01/22/2007 - 01/26/2007 at Grenoble, France

Proceedings: EMLC 2007

Pages: 8Language: englishTyp: PDF

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Thrum, Frank; Kretz, Johannes; Lutz, Tarek; Arndt, Christian; Choi, Kang-Hoon (Qimonda Dresden GmbH & Co. OHG; Koenigsbruecker Straße 180, D-01099 Dresden, Germany)
Keil, Katja (Fraunhofer CNT, Koenigsbruecker Straße 180, D-01099 Dresden, Germany)
Baetz, Ullrich (Fraunhofer IPMS, Maria-Reiche-Str. 2, D-01109 Dresden, Germany)
Belic, Nikola (PDF Solutions GmbH; Schwanthalerstr. 10, D-80336 Munich, Germany)
Lemke, Melchior; Denker, Ulrich; Gramss, Juergen; Kliem, Karl-Heinz (Vistec Electron Beam GmbH; Goeschwitzer Straße 25, D-07745 Jena, Germany)

If electron beam technology is used for direct writing on Si wafers (synonym EBDW) there have to be taken into account a number of specific issues concerning the layout data preparation differing considerably from those of mask writing. This is especially true because EBDW enables the most advanced technology levels which are in general one or two nodes ahead of the mainstream optical lithography. Consequently we will have to face up to additional challenges, such like high resolution and the corresponding CD–control parameters. In order to achieve acceptable turn around times the shaped beam writers have proven to be the tool of choice. To demonstrate this behind a practical background we describe our experiences collected during 300mm wafer exposures with a SB351/3050 tool installed at the Fraunhofer Center Nanoelectronic Technology (CNT) in Dresden/Germany. Appropriate solutions are presented showing how to execute such procedures like layout fracturing and Proximity Effect Correction (PEC) of high-density layouts on a Linux computing cluster. The CD accuracy of lines being of particular interest in connection with sub 50 nm patterns being analyzed and a new model-based method allowing the reduction of the before mentioned effect is evaluated. In any case, whether it is about short or time-consuming exposures, a precise forecast of the total processing time of the wafer in the e-beam exposure tool is of great importance. Practical findings from the use of a simulation tool specifically developed for this purpose are discussed in this paper.