A 10.3125-Gbit/s SiGe BiCMOS Burst-Mode Clock and Data Recovery Circuit with 160-bit Consecutive Identical Digit Tolerance
Conference: ECOC 2007 - 33rd European Conference and Exhibition of Optical Communication
09/16/2007 - 09/20/2007 at Berlin, Germany
Proceedings: ECOC 2007
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Terada, Jun; Nishimura, Kazuyoshi; Togashi, Minoru; Kawamura, Tomoaki; Ohtomo, Yusuke (NTT Microsystem Integration Laboratories, NTT Corporation, 3-1 Morinosato-Wakamiya Atsugi, Kanagawa, 243-0198, Japan)
Kimura, Shunji (NTT Access Network Service Systems Laboratories, NTT Corporation)
A burst-mode clock and data recovery (CDR) circuit for 10 G-EPON OLT receivers is presented. The CDR employs a single-VCO architecutre, which increases consecutive identical digit (CID) tolerance. The developed CDR demonstrates 160-bit CID tolerance.