Effect of polish stopper film in STI-CMP for 45nm node devices and beyond
Conference: ICPT 2007 - International Conference on Planarization / CMP Technology
10/25/2007 - 10/27/2007 at Dresden, Germany
Proceedings: ICPT 2007
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Watanabe, Takashi; Idani, Naoki; Kase, Masataka; Miyajima, Motoshu (Fujitsu Limited, Akiruno Technology Center, 50 Fuchigami, Akiruno, Tokyo, Japan)
Shibata, Seiichi; Nakamura, Makoto; Tamura, Yasuyuki (Fujitsu Laboratories Limited, Akiruno Technology Center, 50 Fuchigami, Akiruno, Tokyo, Japan)
We examined the polishing characteristics when surface oxidized polysilicon (SOPS) is used for the stopper of Shallow Trench Isolation (STI) CMP. The dishing amount of the SOPS stopper process is suppressed effectively compared with that of the SiN stopper process. The stopper loss amount of the SOPS stopper process is also less than that of the SiN stopper process. XPS analysis results show that the polishing process stops at the SiO2 formed on polysilicon without completely removing SiO2. XRF analysis results show that the remaining SiO2 on polysilicon holds a large amount of Ce atoms after CMP. These results indicate that the reduction of the dishing amount and stopper loss is related to the reaction of the SiO2 film formed by the thermal oxidation of polysilicon and Cerium Oxide (CeO2) included in the slurry as an abrasive. The requirements of planarity and stopper loss for STI-CMP in 45 nm node devices are satisfied by the SOPS stopper STI-CMP process. PMOS Vth variation is improved by uniform STI step height of the SOPS stopper process.