Materials Challenges in Planarization and Interconnect Technologies
Conference: ICPT 2007 - International Conference on Planarization / CMP Technology
10/25/2007 - 10/27/2007 at Dresden, Germany
Proceedings: ICPT 2007
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Moinpour, Mansour (Intel Corporation, Global Fab Materials, 2200 Mission College Blvd., Santa Clara, CA)
As integrated circuit device pitches continue to shrink, ultra low k interlayer dielectric (ILD) materials are required to minimize RC signal delay, capacitive coupling noise, and power consumption. The primary thrust of development activities across the industry is introduction of porous low k films with kILD < 2.5. However, these porous materials have significant limitations that make them difficult to integrate with a conventional dual damascene process. This paper reviews some of these significant limitations and performance gaps and surveys development activities currently underway throughout the industry to provide manufacturable solutions. A review of recent published results will focus on the development of dual damascene-compatible pore sealing techniques and methodologies to minimize or reverse ILD etch- and clean- induced damage. The vulnerability of these films to damage from fast ion and radiation damage will be discussed in the context of post-deposition processing (including low-k cure and plasma processing damage). Additionally, planarization challenges for 45nm node and beyond will be discussed in the context of “softer/gentler” polish and new materials that need to be taken into consideration. CMP defectivity challenges in terms of mechanical damage caused by particles will be briefly described. The revolutionary approach such as Carbon Nano Tube (CNT) for BE interconnect will be briefly discussed.