Evaluation of Cu CMP Barrier Slurries for Ultra Low-k dielectric film (k~2.4) for 45nm technology

Conference: ICPT 2007 - International Conference on Planarization / CMP Technology
10/25/2007 - 10/27/2007 at Dresden, Germany

Proceedings: ICPT 2007

Pages: 6Language: englishTyp: PDF

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Zhao, Feng; Li, Jing Hui; Liu, Wu Ping (Chartered Semiconductor Manufacturing Ltd)
Economikos, Laertis; Tseng, Wei-tsu; Engbrecht, Edward; Standaert, Theodorus E.; Nicholson, Lee M.; Sankaran, Sujatha (IBM Systems and Technology Group)
Kim, Hyun-ki (Samsung Electronics Co., Ltd)
Chae, Moosung (Infineon Technologies AG)

Various barrier slurryies for Cu CMP process are evaluated for integratoin of porous ULK (Ultra Low-k, k~2.4) for 45nm technology. The fat-wire dual damascene levels were built with Cu metallization and ULK inter level dielectric. Barrier polishing process removes the remaining etch Hard-Mask and polishes directly into ULK, targeting ~300A removal of ULK film. The study shows that barrier slurries affect the topography, defectivity and within-wafer uniformity. k-value shift measurements on blanket wafers showed that acidic slurry has minimal k-value shift compared to alkaline slurries. However, the k value can be restored with post CMP annealing. k value extracted from integrated wafers using alkaline slurry showed no change due to CMP.