Wafer edge / bevel treatment of device wafers by means of CMP
Conference: ICPT 2007 - International Conference on Planarization / CMP Technology
10/25/2007 - 10/27/2007 at Dresden, Germany
Proceedings: ICPT 2007
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Wieters, Anngret; Thieme, Peter (Process Development CMP, Qimonda Dresden GmbH & Co. OHG, Koenigsbruecker Str. 180, D-01099 Dresden, Germany)
At wafer edge several defects are observed such as flaking, delaminating films, etch damages, metal contaminations and particles etc. These damages and defects are reported and known as root cause for wafer yield loss in edge regions of device wafers. In this paper a special chemical-mechanical polishing (CMP) process was investigated as a very effective method to reduce defect sources at wafer edge of device wafers. In order to see the impact of bevel polish in DRAM production different positions in the process flow with focus on front-end (FEOL) and mid-of- line (MOL) have been tested on different technology nodes. With a bevel inspection the cleanness of the polished bevel was determined. In the following report we will describe the test setup and explain the test results. We will show the effect on cleanness of bevel and entire wafer as well as the impact on yields. Based on our observations the potentials and limitations of bevel polish in comparison to other techniques such as plasma etch treatment or wet clean treatment for yield enhancement will be discussed.