Full-Chip CMP Simulation System

Conference: ICPT 2007 - International Conference on Planarization / CMP Technology
10/25/2007 - 10/27/2007 at Dresden, Germany

Proceedings: ICPT 2007

Pages: 8Language: englishTyp: PDF

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Fukuda, Daisuke; Shibuya, Toshiyuki (Fujitsu Laboratories Ltd. 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan)
Idani, Naoki; Karasawa, Toshiyuki (Fujitsu Limited, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan)

In this paper, we present a Full-chip CMP simulation system. We discuss three problems in practical use of CMP simulation system: how to handle huge chip data, ECP model accuracy, and how to predict the errors effectively. We propose solutions to the problems as follows: First, we develop a data extraction tool from GDSII. Dummy fill insertion function of this tool can reduce the data size of GDSII considerably by removing dummy fill information. Secondly, we propose a refined ECP model for improving accuracy of simulation. Finally, we propose a new method of simulation to predict the errors in the presence of process parameter variations. The variations should be considered, because some of them vary widely and have bad impact on the final chip surface topography. Experimental results show that our tool can extract information for ECP and CMP simulation from large size GDSII data, which a commercial tool may not be able to read. Some data sets that are too large even for our tool to extract from are reduced in size by reducing dummy fill information. Our tool can extract information from these data sets with dummy filling function. The results also show that the new ECP model we proposed has an error of less than 20nm. Our new simulation method can even find CMP process errors that the old method cannot.