Next Generation Barrier CMP technology for 45nm and beyond
Conference: ICPT 2007 - International Conference on Planarization / CMP Technology
10/25/2007 - 10/27/2007 at Dresden, Germany
Proceedings: ICPT 2007
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Ye, Qianqiu Christine; Li, Hugh (Rohm and Haas Electronic Material CMP Technology, 451 Bellevue Road, Newark, DE 19713, USA)
As the IC industry advances to 45nm node in device manufacturing, new materials and processes are being adopted to meet the more stringent performance requirements. Most notably, the dielectric constant, κ, of the dielectric materials is being reduced to 2.5 by incorporating pores into the carbon-doped silicon dioxide (CDO). Porous CDO exhibits weakened mechanical strength and reduced thermal capacity, which present significant challenges to the ensuing process steps. Moreover, leading edge integrated circuits are complicated structures designed to have up to three capping layers above the low K dielectric material. To satisfy these diverse requirements of different designs, a robust barrier slurry family should be able to vary and/or adjust removal rate for each film without adversely affecting other removal rates. Rohm and Haas Electronic Materials has developed a tunable slurry platform. The platform has been developed from an understanding of the basic structure-activity relationships that exist among additives in the slurry and blanket films. A wide range of selectivities have been leveraged from this understanding. The optimization of slurry and advanced pad technology to provide the best processing outcome will be also discussed.