Poly-CMP integration for sub 90 nm self-aligned floating gate flash memories

Conference: ICPT 2007 - International Conference on Planarization / CMP Technology
10/25/2007 - 10/27/2007 at Dresden, Germany

Proceedings: ICPT 2007

Pages: 6Language: englishTyp: PDF

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Mariani, Marcello; Canevari, Luca; Romanelli, Claudia (ST Microelectronics, Via C. Olivetti 2, 20041 Agrate Brianza, Italy)

In this paper, we will show how we solved a strong defectiveness problem that affected high voltage oxide capacitors in our 65 nm node self-aligned floating gate flash memories. While the memory array was successfully planarized and showed a good functionality , the HV oxide capacitors showed a high percentage of failure on wafer, due to very poor QBD. The problem was successfully addressed by individuating and solving three major root causes: - Lifting of micro-crystals embedded in the amorphous silicon matrix (the amount of micro crystals was strongly reduced by reducing the as-deposited α-silicon thickness and modifying the recipe parameters.); - Dishing and loading induced by the structure geometry: after a comprehensive study of the dishing dependence on structures geometry, the capacitors were re-designed to have a CMP-friendly layout; - Dishing and loading effects induced by the slurries used in the CMP process: a totally new CMP process was set-up, using new chemicals. The HV capacitors defectiveness was completely eliminated. By retuning the process integration and re-engineering the poly-CMP process we were thus able to completely set-up a suitable process flow, which preserves both the array and the circuitry performances.