Kang, Young-Jae; Kang, Bong-Kyun; Park, Jin-Goo (Department of Materials Engineering and Bio-nano Technology, Hanyang University, Ansan 426-791, Korea)
Hong, Yi-Koan; Han, Sang-Yeob; Yun, Seong-Kyu; Yoon, Bo-Un; Hong, Chang-Ki (Process Development, Memory Division, Semiconductor Business, Samsung Electronics, Hwasung 445-701, Korea)
Heavily doped poly silicon films have been widely used as gate electrodes and interconnections in MOS circuits because of its compatibility with subsequent high temperature processing, its excellent interface with thermal SiO2, its higher reliability than Al gate materials, and its ability to be deposited conformally over steep topography. The shrinkage of devices below 100 nm requires more stringent and new CMP processes including poly silicon CMP. Poly silicon can be polished easily with similar pads and slurries as they are used for the planarization of silicon oxide. In this study, single crystal and poly silicon wafers were polished as a function of pH in silica based slurry to understand and compare the polishing mechanism of silicon. The static and dynamic etch rates and removal rate were measured as a function of slurry pH (11 ~ 13). The friction force and polishing temperature were also measured at different pHs. The single crystal silicon (bare silicon) showed higher removal rate than the poly silicon. However, higher friction force was measured on poly silicon wafer than on bare wafer.