The Fabrication of Ideal Diamond Disk (IDD) by Casting Diamond Film on Silicon wafer

Conference: ICPT 2007 - International Conference on Planarization / CMP Technology
10/25/2007 - 10/27/2007 at Dresden, Germany

Proceedings: ICPT 2007

Pages: 6Language: englishTyp: PDF

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Sung, James C.; Kan, Ming-Chi; Chang, Hsiao-Kuo (KINIK Company, 64, Chung-San Rd., Ying-Kuo, Taipei Hsien 239, Taiwan, R.O.C.)
Sung, James C. (National Taiwan University, Taipei 106, Taiwan, R.O.C.)
Sung, James C. (National Taipei University of Technology, Taipei 106, Taiwan, R.O.C.)
Chen, Ying-Tung (Department of Mechatronic, Energy and Aerospace Engineering, National Defense University, Tahsi, Taoyuan 335, Taiwan, R.O.C.)
Sung, Michael (Advanced Diamond Solutions, Inc., 351 King Street Suite 813, San Francisco, CA 94158, U.S.A.)

With the relentless densification of interconnected circuitry dictated by Moore’s Law, the CMP manufacture of such delicate wafers requires the significant reduction of polishing pressure, not only globally, but also locally on every tip of individual pad asperities. Conventional diamond disks used for dressing the polyurethane pads cannot produce asperities to achieve such uniformity. A new design of diamond disk was fabricated by casting diamond film on a silicon wafer that contains patterned etching pits. This silicon mold was subsequently removed by dissolution in a hydroxide solution. The diamond film followed the profile of the etching pits on silicon to form pyramids of identical in size and shape. The variation of their tip heights was in microns of single digit that was about one order of magnitude smaller than conventional diamond disks for CMP production. Moreover, the diamond film contained no metal that might contaminate the circuits on polished wafer during a CMP operation. The continuous diamond film could resist any corrosive attack by slurry of acid or base. Consequently, in-situ dressing during CMP is possible that may improve wafer uniformity and production throughput. This ideal diamond disk (IDD) is designed for the future manufacture of advanced semiconductor chips with node sizes of 32 nm or smaller.