Reduction of Dishing in Polysilicon CMP for MEMS Application by Using protective Layer and High Selectivity
Conference: ICPT 2007 - International Conference on Planarization / CMP Technology
10/25/2007 - 10/27/2007 at Dresden, Germany
Proceedings: ICPT 2007
Pages: 5Language: englishTyp: PDF
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Authors:
Shin, Woonki; Park, Kihyun; Joo, Sukbae; Jeong, Haedo (Department of Mechanical and Precision Engineering, Pusan National University, Busan 609-735, Korea)
Park, Sungmin (Dept. of Mechanical Engineering, University of California at Berkeley, CA, USA)
Kim, Hyoungjae (Busan R&D Center, Korea Institute of Industrial Technology, Busan 609-735, Korea)
Abstract:
The aim of this paper is to develop the planarization process to make flat surface in patterned areas for multilevel MEMS devices using CMP process. With creating planar surface in each layer, the accuracy and flexibility of following steps such as lithography, etching and/or deposition process can be drastically enhanced. For this purpose, the two step CMP process has been developed. The 30nm thick protective oxide layer was deposited to protect recessed areas. The wafer with protective layer is then polished with low selectivity slurry to partially remove protruded area while suppressing the removal rate of the recessed area. After the first step CMP process, high selectivity slurry was used to minimize the dishing amount and variation in pattern structures. Experimental results show that the dishing amount was less than 30nm at the largest pattern of 1250um wide and had no variation in whole patterns, which means local and global planarization. This result suggests that the developed two step CMP process can be successfully applicable to fabricate the multilevel MEMS device.