Damascene Metal Gate Technology: A Front-end CMP Based Universal Platform for High-k Evaluation at the Device Level
Conference: ICPT 2007 - International Conference on Planarization / CMP Technology
10/25/2007 - 10/27/2007 at Dresden, Germany
Proceedings: ICPT 2007
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Endres, Ralf; Schwalke, Udo (Institute for Semiconductor Technology and Nanoelectronics, Technische Universität Darmstadt, D-64289 Darmstadt, Germany)
This paper presents the first successful attempt to integrate crystalline high-K gate dielectrics into a virtually damage-free damascene metal gate process by means of frontend chemical mechanical planarization. Process details as well as initial electrical characterization results on fully functional gate Gd2O3 dielectric MOSFETs with equivalent oxide thickness (EOT) down to 1nm are discussed.