Topological and Model Based approach to Pitch decomposition for Double Patterning

Conference: EMLC 2008 - 24th European Mask and Lithography Conference
01/21/2008 - 01/24/2008 at Dresden, Germany

Proceedings: EMLC 2008

Pages: 12Language: englishTyp: PDF

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Nikolsky, Peter; Davydova, Natalia (ASML Netherlands B.V.)
Goossens, Ronald (Brion Technologies, an ASML company)

Double Patterning (DP) is one of the main enabling technologies for expanding Photolithography beyond 40nm technology node. Geometrical pitch split is the core of DP. It is known and reviewed in this paper that not all sub-resolution layouts can be successfully split to two DP masks, so a method for early Design for Manufacturability (DfM) check is strongly required. New accurate, efficient and Litho-aware methods for DP also minimize number of split errors and “false alarms” typical for Rule-Based Mask Data Preparation for Double Patterning. In this paper we proposed the topological approach (Model assisted Topological Rules Check, MTRC) to the pitch decomposition for Double Patterning based on Litho process modeling and real Litho resolution of a process. This method allows to find features below a resolution limit of a process and automatically sort them between DP-friendly and DP-unfriendly (DfM check for requiring redesign, “native conflicts”, NC) cases. MTRC helps to improve DP-unfriendly designs in optimal way at early stage and avoid costly feedback loops. The second part of the paper explains the Model based DP pitch decomposition algorithm based on layout printability. It performs accurate and efficient split of various patterns with k1<0.25 to two masks with k1>0.25 as an integrated part of the Mask Data Preparation flow. The developed algorithm of Model based DP pitch decomposition allows error-free split of patterns below the resolution limit of the Litho system to two DP masks with sufficient printability confirmed by simulations and MTRC. The analysis of performance of the complex MB DP split approach mentioned above was performed on a selection of clips representing generic designs and typical Flash, DRAM, SRAM and Logic polygon shapes.