3D Wafer Level System Integration – Requirements & Technologies
Conference: Smart Systems Integration 2008 - 2nd European Conference & Exhibition on Integration Issues of Miniaturized Systems - MOMS, MOEMS, ICS and Electronic Components
04/09/2008 - 04/10/2008 at Barcelona, Spain
Proceedings: Smart Systems Integration 2008
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Klumpp, A.; Wolf, M. J.; Ramm, P.; Wunderle, B.; Reichl, H. (Fraunhofer IZM, Berlin/München, Germany)
3D integration is a fast growing field that encompasses different types of technologies. The paper addresses one of the most promising technology which uses Through Silicon Vias (TSV) for interconnecting stacked devices on wafer level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM has developed a post front-end 3D integration process which allows stacking of functional and tested FE-devices e.g. sensors, ASICs on wafer level as well as a technology portfolio for passive silicon interposer with redistribution layers and TSV.