Implantable Packaging Technique Featuring Through Wafer Interconnects and Low Temperature Direct Bond

Conference: Smart Systems Integration 2008 - 2nd European Conference & Exhibition on Integration Issues of Miniaturized Systems - MOMS, MOEMS, ICS and Electronic Components
04/09/2008 - 04/10/2008 at Barcelona, Spain

Proceedings: Smart Systems Integration 2008

Pages: 6Language: englishTyp: PDF

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Lee, James (Applied Microengineering Ltd, Didcot, Oxfordshire, UK)

A novel packaging method is presented for an implantable, biocompatible smart system to provide through wafer interconnects to a CMOS chip encapsulated with a vacuum compatible low temperature silicon-silicon direct bond carried out at 200?? thus avoiding damage to the chip. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for implanted integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through wafer interconnection. The proposed embodiment of this method features a 2-channel mixed signal ASIC (records and stimulates neural activity), bump bonded directly onto solid gold electroplated through wafer interconnects on a carrier wafer. The silicon encapsulation wafer is bonded to the carrier wafer using a direct bond for which strength and hermeticity are achieved by activating surfaces with free radicals prior to bonding. This bond is annealed to full strength at 200?? ensuring no damage to the ASIC. Onto the back of the packaged wafer, a layer of PDMS is spin coated and flexible, low resistance active circuits and electrodes are metallised using excimer laser ablation and selective plating in an autocatalytic platinum bath. The circuits are encapsulated in a further layer of PDMS before dicing. Solid electroplated through wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. Many of the processes used in this construction will have wider applicability in wafer level packaging.