A new method for wafer level integration of silicon components on LTCC
Conference: Smart Systems Integration 2008 - 2nd European Conference & Exhibition on Integration Issues of Miniaturized Systems - MOMS, MOEMS, ICS and Electronic Components
04/09/2008 - 04/10/2008 at Barcelona, Spain
Proceedings: Smart Systems Integration 2008
Pages: 3Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Bartsch de Torres, H.; Fischer, M.; Gade, R.; Mach, M.; Müller, J.; Hoffmann, M. (Technische Universität Ilmenau, Institute for Micro- and Nanotechnologies, Germany)
Pawlowski, B.; Barth, S. (HITK e.V. Hermsdorf, Germany)
Reliable packaging of MEMS devices is a cost intensive step in the fabrication process. Hybrid packages require complex and thus costly assembly and test procedures. Monolithic packages with reduced thermal coefficient of expansion (TCE) mismatch are only profitable for large lot sizes. Additionally, the semiconducting behaviour of the bulk silicon substrate limits the device performance. The silicon-on-insulator (SOI) technology overcomes this limitation by an insulating SiO2.layer Based on this principle, the silicon-onceramics (SiCer) technology uses insulating ceramics as substrate. LTCC (Low Temperature Cofired Ceramics) can easily be patterned in the green state. Vias and fluidic channels can be produced and after lamination and co-sintering with a silicon wafer a customised hybrid substrate is available, which already contains electrical and fluidic interfaces. Unwanted silicon can be removed easily by standard silicon etching, hereby the ceramic works as an etching barrier. Device or system packaging is achieved on wafer level.