Time-dependent reliability of ultra-scaled CMOS devices and its impact on circuit performance
Conference: Smart Systems Integration 2008 - 2nd European Conference & Exhibition on Integration Issues of Miniaturized Systems - MOMS, MOEMS, ICS and Electronic Components
04/09/2008 - 04/10/2008 at Barcelona, Spain
Proceedings: Smart Systems Integration 2008
Pages: 3Language: englishTyp: PDF
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Authors:
Martín-Martínez, J.; Rodríguez, R.; Nafría, M. (Dept. Eng. Electrònica, Universitat Autònoma de Barcelona, Bellaterra, 08193 Barcelona, Spain)
Gerardin, S.; Paccagnella, A.; Aymerich, X. (DEI Universita di Padova, via Gradenigo 6/B Padova, Italy)
Ghidini, G. (ST Microelectronics, via C. Olivetti 2, 20041 Agrate Brianza, Italy)
Abstract:
Technology scaling has enabled increased speed, lower energy consumption and lower die cost. However, new reliability issues appear in these deep sub-micron technologies. The aging of devices during circuit operation will have to be considered during the circuit design phase, so that models that represent the modified behaviour of devices will be needed. In this work, the wear-out of the gate dielectric of MOS devices during electrical stress and its impact on the performance of devices and circuits are addressed. As an example of gate degradation impact on circuits, the wear-out effects in an inverter have been studied.