A Fault-Tolerant Processor Architecture

Conference: ARCS 2009 - 22th International Conference on Architecture of Computing Systems
03/11/2009 at Delft, The Netherlands

Proceedings: ARCS 2009

Pages: 6Language: englishTyp: PDF

Personal VDE Members are entitled to a 10% discount on this title

Bouajila, Abdelmajid; Sommer, Thomas; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas (Institute for Integrated Systems, Technische Universität München, Arcisstr. 21, 80290 München, Germany)

This paper presents a new architecture for Fault-Tolerant processor design inspired from the DIVA technique. DIVA consists of inserting a checker unit in front of the processor commit stage. The checker unit re-executes both computation and memory/register file reads. Whenever an error is detected, the original DIVA checker which is assumed to be fully reliable fixes the error, then commits results (i.e. writes them to memory/register file), flushes the processor and restarts it at the next instruction. In our Modified DIVA architecture, we no longer assume that the checker is fully reliable. In case of error detection, the processor is flushed and restarted at the erroneous instruction. Therefore our modified architecture is more reliable. In order to increase performance, we protect external memory reads with ECC, our checker unit does not re-execute them and therefore the checker and processor are no longer competing for memory accesses as was the case in original DIVA. We have also extended the application of the DIVA technique to a standard RISC pipelined processor (original DIVA was mainly aimed at Superscalar architectures). These new architectural improvements in comparison to original DIVA are presented in this paper, and VHDL implementation results are reported. Fault injection in VHDL simulations was used to evaluate this new technique.