Efficient Fault-Tolerant Addition by Operand Width Considerat
Conference: ARCS 2009 - 22th International Conference on Architecture of Computing Systems
03/11/2009 at Delft, The Netherlands
Proceedings: ARCS 2009
Pages: 3Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Fechner, Bernhard; Keller, Jörg (FernUniversität in Hagen, Dept. of Mathematics and Computer Science, 58084 Hagen, Germany)
Addition is a central operation in microcontrollers and hence faults should be detected for safety reasons. We extend the principle of recomputing with shifted operands (RESO) by doing the re-computation concurrently to the computation in the case of small operands. Thus, we generate a solution cheaper than two adders and faster than simple repetition. To extend RESO, we consider the actual bit-widths of the operands. We validate our method with data from static code analysis of two application kernels.