Petri Net Analysis of Non-Redundant and Redundant Execution Schemes
Conference: ARCS 2009 - 22th International Conference on Architecture of Computing Systems
03/11/2009 at Delft, The Netherlands
Proceedings: ARCS 2009
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Einer, Stefan (Schweizerische Bundesbahnen, 3000 Bern, Switzerland)
Fechner, Bernhard; Keller, Jörg (FernUniversität in Hagen, 58084 Hagen, Germany)
The quest for high-performance has led to multi- and many-core systems. To push the performance of a single core to the limit, simultaneous multithreading (SMT) is used. SMT enables to fetch different instructions from different threads, hiding latencies in other threads. SMT also gives the opportunity to execute redundant threads (redundant multithreading, RMT) and thus to detect faults by comparing the results of both threads. The instruction fetch algorithm determines which instructions to fetch from which thread and therefore has great influence on processor performance. This work investigates the influence of different instruction fetch algorithms on the performance of an SMT processor by modeling it with Petri nets. Over the intrinsic results of a detailed processor simulation, our approach offers a generic evaluation. Furthermore, we distinguish between homogeneous (redundant execution, RMT) and inhomogeneous threads to determine the effects on the performance of each execution scheme with a dedicated instruction fetch algorithm. For inhomogeneous threads, the effect of instruction fetch algorithms can be confirmed, but not for homogeneous threads. Therefore, scheduling algorithms as simple as Round Robin can be recommended for redundant execution.