Waveform-based Timing Analysis for Digital Circuits using Current Source Models and Model Order Reduction

Conference: edaWorkshop 09 - Workshop 2009 - Electronic Design Automation (EDA)
05/26/2009 - 05/28/2009 at Dresden, Germany

Proceedings: edaWorkshop 09

Pages: 6Language: englishTyp: PDF

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Knoth, Christoph; Kleeberger, Veit B.; Chen, Ning; Schlichtmann, Ulf (Institute for Electronic Design Automation, Technische Universität München)
Nordholz, Petra (Infineon Technologies AG, Neubiberg)

Timing analysis of digital integrated circuits requires more precise methodologies to account for analog effects. One method is waveform-based timing analysis which considers the real voltage waveforms instead of idealized ramp models, leading to more accurate results. However, analog circuit simulation is needed to calculate the output waveforms. For the complexity of industrial digital circuits, this is far too time consuming. This paper addresses the performance bottleneck and presents an approach to perform SPICE simulation on gate level including interconnect models. While almost preserving SPICE accuracy, simulation times could be reduced by up to 90%. This is achieved by two means. First, mature linear model order reduction techniques are applied to high dimensional interconnect structures to reduce the number of differential equations. However, for typical interconnects the simulation time reduction is below 5%. The second means is to employ newly developed current source models (CSMs). These CSMs are used to replace the transistor descriptions of logic cells. The models store the gate output current in a lookup-table dependent on the port voltages. Therefore, expensive evaluation of transistor equations is avoided. For characterizing CSMs a novel and much simplified method is presented. The acceleration techniques have been implemented into a standard SPICE simulator. Results, also for non-ideal input waveforms, show both accuracy and a significant performance gain.