A Rapid Prototyping Environment for ASIP Validation in Wireless Systems
Conference: edaWorkshop 09 - Workshop 2009 - Electronic Design Automation (EDA)
05/26/2009 - 05/28/2009 at Dresden, Germany
Proceedings: edaWorkshop 09
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Alles, Matthias; Lehnigk-Emden, Timo; Brehm, Christian; Wehn, Norbert (Microelectronics Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany)
Current and future wireless devices have to contain flexible outer modems in order to support the many different communication standards used today. Application-specific instruction-set processors (ASIPs) are promising candidates to deliver this flexibility with low power and small silicon area. Their high flexibility allows to support a vast number of different standards. However, testing of such ASIPs is very challenging. Statistical simulations are required, meaning that only after running the channel decoder for many thousand blocks it can be considered to be working correctly. Simulation on nowadays PCs lacks at least three orders of magnitude in throughput. In this paper we present an ASIP prototyping platform, that validates an ASIP in conjunction with its running programs. The ASIP and its baseband processing environment (encoder, modulator, noise channel, etc.) are mapped into an FPGA-based prototyping platform to perform hardware accelerated emulation. Compared to software simulation of the processor pipeline on state-of-the-art computers we could achieve speed improvements of three orders of magnitude.