Multi-bit Soft- and Timing Error Detection for CPU Pipelines
Conference: edaWorkshop 09 - Workshop 2009 - Electronic Design Automation (EDA)
05/26/2009 - 05/28/2009 at Dresden, Germany
Proceedings: edaWorkshop 09
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Bouajila, Abdelmajid; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas (Technische Universität München, Arcisstrasse 21, München 80290, Germany)
In this work-in-progress paper we present a new scheme for multiple soft- and timing error monitoring in CPU pipelines. This scheme is based on combining a time redundancy technique (schadow register) and an information redundancy technique (Error Detecting and Correcting Codes). The scheme fault coverage includes multiple transient (SET, SET) and timing errors. The use of this scheme in building self-correcting CPU pipelines will be then presented.