Methodology and Tools for Simulation-Based Crosstalk Analysis in RF and Mixed Signal SoC's and SiP's
Conference: edaWorkshop 10 - Workshop 2010 - Electronic Design Automation (EDA)
05/04/2010 - 05/05/2010 at Hannover, Germany
Proceedings: edaWorkshop 10
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Brenner, P. (Infineon Technologies AG, Design Methodology & Implementation, Analog Design Methodology Department)
Knöchel, U. (Fraunhofer-IIS, Design Automation Division (EAS)
This paper will present a new methodology which enables analog circuit simulations and analog verification of complex radio transceiver chips. RF and analog performance on silicon is always degenerated by crosstalk (XT) and parasitic interference effects which inevitable emerge from the physical design implementation (block design, layout, substrate, floorplan, package and PCB). Basic physical causes for crosstalk, signal integrity (SI) and interoperability (IOP) problems are resistive, capacitive or inductive coupling effects between critical circuit nets. The parasitic resistance, capacitance and inductance of the wiring and isolation layers can be extracted but leads to extremely complex netlists which can not be simulated. A problem-tailored combination of powerful netlist reduction and netlist post-processing tools with a semi-automated circuit block (CB) modeling flow enables complexity reduction of up to three orders of magnitude. Extracted views with all parasitic elements, recently not simulatable, can now be simulated with powerful analog/RF circuit simulators. The aim of our complexity reduction approach is to enable analog circuit simulations on signal path or system level. Therefore we apply suitable model order reduction (MOR) methods which can identify and include critical parasitic effects from physical design implementation. These MOR methods will on the other hand remove minor implementation parasitics. In this way parasitic crosstalk effects, which seriously degenerate overall circuit performance, can be identified by simulation and can be fixed before tapeout.