Impact of power management on temperature and reliability evolution for an embedded many-core architecture
Conference: ARCS 2011 - 24th International Conference on Architecture of Computing Systems
02/22/2011 - 02/23/2011 at Como, Italy
Proceedings: ARCS 2011
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Carbon, M. Alexandre; Chehida, Karim Ben; David, Raphaël (CEA, LIST, Embedded Computing Lab, Gif-sur-Yvette, 91191, France)
Héron, Olivier (CEA, LIST, Embedded System Reliability Lab, Gif-sur-Yvette, 91191, France)
Technology scaling and the increasing demand for performance have led to the development of many-core architectures in order to exploit parallelism and to avoid physical limits which started to appear in mono-processors (especially in terms of performance and power consumption). Although the design of these architectures is less aggressive (timing closure), the non-ideal technology scaling leads to an increase of power densities which cause chip temperature (hotspots, gradients) and reliability problems (faster aging and frequent intermittent errors). There is a strong relationship between reliability, temperature, power and performance. The presence of thermal hotspots and gradients (spatial and temporal) affects significantly the chip performance, power consumption, cost and reliability. The transistor switching and interconnect delays increase with temperature. Moreover, a temperature increase causes an increase in leakage power that also causes a temperature increase. This positive feedback loop can lead to chip destruction if the power dissipation is not controlled.