Trading Fault-Masking with Performance Overhead for FPGAs
Conference: ARCS 2011 - 24th International Conference on Architecture of Computing Systems
02/22/2011 - 02/23/2011 at Como, Italy
Proceedings: ARCS 2011
Pages: 4Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Siozios, Kostas; Soudris, Dimitrios (School of Electrical and Computer Engineering, National Technical University of Athens, Greece)
Reliability issues become an important design concern with technology scaling. This paper introduces a novel methodology for balancing the desired fault masking and the consequence delay and power overheads due to redundancy. Experimental results shown that our solution outperforms similar approaches since it achieves average delay and power savings up to 25% and 35%, respectively, for comparable fault masking to existing commercially available solutions.