Fault tolerant multiplication based on convolution
Conference: ARCS 2011 - 24th International Conference on Architecture of Computing Systems
02/22/2011 - 02/23/2011 at Como, Italy
Proceedings: ARCS 2011
Pages: 5Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Signes Pont, Maria Teresa; Mora Mora, Higinio; García Chamizo, Juan Manuel (Dpt. Tecnología Informática y Computación, Universidad de Alicante, Spain)
This paper presents a new approach to the multiplication for signed numbers in two’s complement which can achieve different levels of fault tolerance by combining hardware and time redundancy. The partial products are considered as convolutions between two discrete functions and carried out by addressing recursively a Look-up table where they have been stored. The self-checking capability is achieved by the parallel calculation of two different but equivalent convolutions. The fault tolerance for transient errors is achieved by using time redundancy in each convolution thread. A very simple circuit implements the multiplier which provides encouraging results in hardware overhead compared with other well-known proposals. This paper is devoted to expose the method, development, capabilities and implementation.