Software Fault-Tolerant Techniques for Softcore Processors in Commercial SRAM-Based FPGAs

Conference: ARCS 2011 - 24th International Conference on Architecture of Computing Systems
02/22/2011 - 02/23/2011 at Como, Italy

Proceedings: ARCS 2011

Pages: 4Language: englishTyp: PDF

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Rollins, Nathaniel H.; Wirthlin, Michael J. (NSF Center for High-Performance Reconfigurable Computing (CHREC), Department of Electrical and Computer Engineering, Brigham Young University, Provo, UT. 84602, USA)

This paper implements software fault-tolerant techniques on a softcore processor implemented in a commercial SRAM-based FPGA for use in space-based applications. These software techniques include a modified version of software implemented fault tolerance (SWIFT), consistency checks, and checkpointing. To evaluate the reliability and costs of using software techniques to protect a softcore processor, two popular hardware-based techniques are used for comparison: duplication with compare (DWC) with checkpointing, and triple modular redundancy (TMR) with checkpointing. All of these techniques are implemented on the LEON3 softcore processor - the processor used by the European space agency (ESA). In this paper we protect the LEON3 softcore processor against SEUs at the cost of time instead of area. This goal is accomplished by using software fault-tolerant techniques. This study shows that specific software mitigation techniques can detect and recover from 99% of all configuration upsets to the LEON3 processor at a third the area cost of TMR, and for only a 1.8x performance cost.