Customizing a VLIW Chip Multiprocessor for Motion Estimation Algorithms

Conference: ARCS 2011 - 24th International Conference on Architecture of Computing Systems
02/22/2011 - 02/23/2011 at Como, Italy

Proceedings: ARCS 2011

Pages: 7Language: englishTyp: PDF

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Chouliaras, V.; Stevens, D. (Department of Electronic and Electrical Engineering, Loughborough University, Loughborough, UK)
Lentaris, G.; Reisis, D. (Electronics Laboratory, Department of Physics, National and Kapodistrian University of Athens, Physics Bld IV, Athens 15784, Greece)

This paper discusses the customization of the LE1 VLIW Chip Multiprocessor (CMP) for processing Motion Estimation (ME) algorithms in video coding applications. The LE1 is based on an 8-stage pipeline, configurable, extensible VLIW core implementing a partially-predicated Instruction Set Architecture (ISA) with support for pipelined, multi-input, multi-output (MIMO) custom instruction extensions and a shared-memory programmer's model. The CMP is parameterizable with respect to the number of processors, their architectural (issue) width, the setting of features at the micro-architecture level, such as the latency and the local memory system and the mix of the functional units. The results of this work demonstrate the efficiency of the processor when executing video coding kernels such as Motion Estimation; the CMP achieves near-linear speed-up in the computation of a number of such ME algorithms including Full Search, Three Step Search, Diamond Search, and PMVFAST. FPGA implementations are also presented.