Evaluating Static CMOS Complex Cells in Technology Mapping
Conference: ARCS 2011 - 24th International Conference on Architecture of Computing Systems
02/22/2011 - 02/23/2011 at Como, Italy
Proceedings: ARCS 2011
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Pilato, Christian; Ferrandi, Fabrizio (Politecnico di Milano, Dipartimento di Elettronica ed Informazione, Milano, Italy)
Pandini, Davide (STMicroelectronics, Central CAD and Design Solutions, Agrate Brianza, Italy)
Current EDA tools are often based on standard-cell libraries for the design of modern complex systems-on-chip. In general, the composition of such libraries does not follow a fixed rule, but it is mainly based on the experience of the chip foundries. They compact or extend the standard cell libraries by removing or adding certain implementations, respectively, in order to optimize specific goals (e.g., area, timing or power consumption) or a specific set of designs. In this paper, we define and present a comprehensive study about the effects of using static CMOS complex gates in technology mapping. The impact of such cells has been evaluated on several benchmarks usually adopted in logic synthesis targeting a 45nm technology with Synopsys Design Compiler.