Transistor Sizing Analysis of Regular Fabrics
Conference: ARCS 2011 - 24th International Conference on Architecture of Computing Systems
02/22/2011 - 02/23/2011 at Como, Italy
Proceedings: ARCS 2011
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Marranghello, Felipe S.; Bem, Vinicius Dal; Reis, André I.; Ribas, Renato P. (UFRGS, Porto Alegre, Brazil)
Moll, Francesc (UPC, Barcelona, Spain)
This paper presents an extensive transistor sizing analysis for regular transistor fabrics. Several evaluation methods have been exploited, such as DC simulations, ring oscillators and single-gate open chain structures. Different design aspects are addressed taking into account stacked transistors, cells with drive strengths and circuit critical paths. The performance degradation of using regular fabrics in comparison to standard cells is naturally expected, but it is quite important to evaluate the dimension of such impact. The results were obtained for predictive PTM45 CMOS parameters, and the conclusions can be easily extrapolated to other technology nodes and fabrication processes.