Reliability Optimization of Analog Circuits with Aged Sizing Rules and Area Trade-off
Conference: edaWorkshop 11 - Proceedings
05/10/2011 - 05/12/2011 at Dresden, Germany
Proceedings: edaWorkshop 11
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Pan, Xin; Graeb, Helmut (Institute for Electronic Design Automation, Technische Universitaet Muenchen, Germany)
Manufacturing process induced parameter variations and lifetime condition dependent parameter degradations (aging) are two major hurdles limiting the reliability of analog circuits. While the two issues were mainly considered separately by various communities in the past, analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects. This paper proposes an efficient method based on worst-case distance and aged sizing rules checking to analyze and optimize the analog circuits. The trade-off between the design robustness and the price we pay, such as circuit area, is studied in detail. Furthermore, the paper applies a time domain prediction model based on sensitivity analysis to predict the lifetime worst-case distance, for designers to get a quick image about their design robustness over lifetime. Experimental results show that a more robust design can be achieved by increasing the total area by 27%. The applied prediction method is eight times faster in comparison to the lifetime yield analysis method by an optimization solver.