Systematic fault simulation of a fault tolerant NoC
Conference: edaWorkshop 12 - Workshop 2012 - Electronic Design Automation (EDA)
05/08/2012 - 05/09/2012 at Hannover, Germany
Proceedings: edaWorkshop 12
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Lu, Weiyun; Radetzki, Martin (Institut fuer Technische Informatik - Stuttgart University, Pfaffenwaldring 47, 70569 Stuttgart, Germany)
In this paper we perform a systematic system-level fault simulation of a fault tolerant design. The two fault models used are permanent single link fault and permanent single crossbar fault. In the conventional method, a subset of faults is randomly selected and fault simulation is only performed for those selected faults. In our method instead, for each fault model, all possible faults are simulated in one round with a concurrent and comparative fault simulator, thus to obtain a thorough overview and more detailed analysis of all the faults. Throughput, latency and simulation speedup are analyzed with respect to fault models, NoC sizes, traffic patterns and traffic injection rates.