Compilation of Methodologies to Speed up the Verification Process at System Level

Conference: edaWorkshop 12 - Workshop 2012 - Electronic Design Automation (EDA)
05/08/2012 - 05/09/2012 at Hannover, Germany

Proceedings: edaWorkshop 12

Pages: 6Language: englishTyp: PDF

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Radke, Stephan; Rülke, Steffen; Fehlauer, Erhard (Fraunhofer EAS/IIS)
Oliveira, Marcio F. S.; Kuznik, Christoph; Müller, Wolfgang (University of Paderborn/C-LAB)
Ecker, Wolfgang; Esen, Volkan (Infineon Technologies)
Hufnagel, Simon; Bannow, Nico; Oetjens, Jan-Hendrik (Robert Bosch GmbH)
Brazdrum, Helmut; Janssen, Peter (Tieto ES GmbH)
Le, Hoang M.; Große, Daniel; Haedicke, Finn (University of Bremen)
Drechsler, Rolf (University of Bremen )
Koch, Gernot (Micronas)
Burger, Andreas; Bringmann, Oliver (Forschungszentrum Informatik)
Rosenstiel, Wolfgang (University of Tübingen)
Görgen, Ralph (OFFIS)

This paper describes the ongoing research of significant performance enhancements in the simulation-based verification process at electronic system level. In this challenging field, there is more than one way to improve the verification process. Hence, a compilation is presented which contains seven novel or enhanced approaches respectively. Each of it addresses another subdomain in the field of simulation-based verification. Every individual approach targets to reduce the process time in that subdomain. Utilizing them united, the approaches afford a significant performance benefit. Most of this work has been accomplished in the SANITAS project that is partly funded by the German Federal Ministry of Education and Research (BMBF).