NBTI Effects on Clock Uncertainty and Applications in Continuous-Time Σ-Δ Modulator

Abstract:
This paper discusses Negative Bias Temperature Instability (NBTI) mechanism and its effect to 65 nm CMOS integrated circuits and systems. For reliability simulation in large and complex analog/mixed signal (AMS) systems, a hierarchical flow containing transistor-level reliability simulation and behavioral system-level simulation is used to evaluate performance degradation. Simulation results show that NBTI can cause clock uncertainties in form of clock skew or jitter in a non-overlapping clock distributor circuit designed in a 65 nm CMOS technology. A study of a continuous-time (CT) σ-δ (?Δ) modulator is demonstrated to evaluate NBTI effects on a complete system. Results show that ageing risk exists in clock circuits when they are implemented with high threshold voltage (VT ) transistor model. NBTI induced clock jitter from clock distributor can influence clocked block in CT ?Δ modulator and severely degrade signal-to-noise ratio (SNR).