FALP: A Fault Adaptive and Low Power Method for Network on Chip Router
Conference: ARCS 2014 - 27th International Conference on Architecture of Computing Systems
02/25/2014 - 02/28/2014 at Luebeck, Deutschland
Proceedings: ARCS 2014
Pages: 7Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Mohammadian, Farhad (Department of Computer Engineering and Information Technology, Amirkabir University of Technology, Iran)
Network-on-Chip (NoC) are known as the future communication infrastructure for many-core systems. They are susceptible to malfunction in the presence of the faults as technology sizes scales down, which reduces the performance of the system. According to the experimental results of this article, links have failed 71% of the time when Crosstalk fault has occurred, highlighting the importance of the reliable links. A new fault-tolerant and low power, calling FALP, method for NoC routers is presented in this article to mitigate their unexpected behavior through links. It minimizes switching power consumption overhead by keeping track of the frequency and life time of faults. The experimental and analysis results show that FALP has 11% area overhead of router component rather than Hamming method. However, based on the VHDL implementation of a NoC router, routing unit has a negligible area comparing to other components of an NoC router. In a router architecture less than 11% of an NoC router area is occupied by routing component embedded with FALP technique, while the proposed method reduces 3% to 16% power consumption comparing to Hamming transmission.