Towards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based Multiprocessors
Conference: ARCS 2014 - 27th International Conference on Architecture of Computing Systems
02/25/2014 - 02/28/2014 at Luebeck, Deutschland
Proceedings: ARCS 2014
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Derin, Onur; Fiorin, Leandro (ALaRI, Faculty of Informatics, University of Lugano, Via G. Buffi 13, 6904, Lugano, Switzerland)
In order to satisfy performance and low power requirements of applications, embedded systems are becoming increasingly complex and highly integrated with various types of cores. As complexity increases and CMOS technology scales down into the deep-submicron domain, the rate of hard and soft faults in such systems increases. Such trend requires the reliability aspect to be incorporated as a design goal along with the more conventional goals such as performance, cost and power. In this paper, we investigate the reliability achieved by two system-level fault tolerance techniques, namely online task remapping and N-modular redundancy. By means of an analytical model of applications represented as Kahn Process Networks running on heterogeneous multiprocessors based on Networks-on-Chip, we evaluate these techniques with respect to the obtained level of reliability (mean-time-to-failure) and the overhead in computation (execution time) and communication (amount of data transfer on the network). By presenting a reliability estimation method, we enable a reliability-aware design flow on NoC-based MPSoCs.