A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM

Conference: ARCS 2014 - 27th International Conference on Architecture of Computing Systems
02/25/2014 - 02/28/2014 at Luebeck, Deutschland

Proceedings: ARCS 2014

Pages: 5Language: englishTyp: PDF

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Matsukawa, Go; Nakata, Yohei; Kimi, Yuta; Kawaguchi, Hiroshi; Yoshimoto, Masahiko (Graduate School of System Informatics, Kobe University, Kobe, Japan)
Sugure, Yasuo (Central Research Laboratory, Hitachi, Ltd., Yokohama, Japan)
Shimozawa, Masafumi (Hitachi Solutions, Ltd., Yokohama, Japan)
Oho, Shigeru (Department of Electrical and Electronics Engineering, Nippon Institute of Technology, Minamisaitama, Japan)
Yoshimoto, Masahiko (Japan Science and Technology Agency (JST) CREST, Tokyo, Japan)

This paper presents a novel architecture for a fault-tolerant high-performance system using a checkpoint/restart approach with dual modular redundancy (DMR). The proposed architecture can perform low-latency copy with instantaneously copiable SRAM. Furthermore, we can use an instantaneous comparison scheme that has more fault coverage than comparison with a cyclic redundancy check (CRC). Evaluation results show that, compared with the conventional checkpoint/restart DMR, the proposed architecture reduces the cycle time by 97.8% and achieves a 3.28% low-latency execution cycle even if a one-time fault occurs when executing the task.