SiC-JFET in half-bridge configuration – parasitic turn-on at current commutation
Conference: PCIM Europe 2014 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
05/20/2014 - 05/22/2014 at Nürnberg, Deutschland
Proceedings: PCIM Europe 2014
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Heer, Daniel; Bayerer, Reinhold; Domes, Daniel (Infineon Technologies AG, Germany)
This paper describes the effect of parasitic turn-on in SiC-semiconductors. The device under test is a half-bridge with 1700V normally-on SiC-JFETs. The half bridge contains 32 chips in parallel, 64 chips in total, resulting in a current rating of 480A. The module design follows the strip-line concept as published in . Parasitic inductance in the power circuit amplifies the effect of parasitic turn-on. Gate inductance outside the module as well the inductance of gate and source sub-circuits inside the module play an important role in minimizing the parasitic turn-on [2, 3, 4]. To fully utilize SiC-devices in fast switching applications, an overall low inductance design is absolutely required. Thus, in combination with a special gate-drive concept, the effect of the parasitic turn-on will be reduced. The SiC-JFET shows superior performance in terms of switching losses even with some parasitic turn-on.