Physical Design with a Critical Area Methodology
Conference: edaWorkshop 14 - Tagungsband
05/13/2014 - 05/14/2014 at Hannover, Germany
Proceedings: edaWorkshop 14
Pages: 7Language: englishTyp: PDF
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Authors:
Colomb, Jean-Pierre (Oasic Design Automation, 3, Chemin du vieux chêne 38240 Meylan, France)
Silvant, Mathias (EdXact SA, Parc Work Center, 8, Route des bois, 38500 Voiron, France)
Gary, Marjorie (CEA-Leti, 17 rue des Martyrs, 38054 Grenoble, France)
Abstract:
Increasing the yield of advanced integrated circuits with a high degree of reliability is a demanding task. The analysis of critical layout areas early in the design flow is a technique that is very promising in order to find and rework the so-called hot spots. In this paper, we describe practical implementations of a layout analysis flow that allows finding hot spots. Two versions are presented: a first one only relies on the geometry, while a second one takes into account the electrical information after LVS. The flows have been evaluated on industrial grade circuits using a wide range of process and show promising results.