New MOSFET Packaging Techniques for High Power Density
Conference: PCIM Asia 2015 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
06/24/2015 - 06/26/2015 at Shanghai, China
Proceedings: PCIM Asia 2015
Pages: 8Language: englishTyp: PDF
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Authors:
Lee, Chien-Hsun; Billings, David; Wen, Yenting (ON Semiconductor, Phoenix, AZ, USA)
Abstract:
Present synchronous buck loss model with parasitic inductance is not sufficient to account for power losses especially with sub-milliohm high output capacitance synchronous MOSFETs. Output capacitance impact on hard switching is explained and verified. A new model including parasitic inductance and capacitance effects is presented here. New packages minimizing common source inductance and maximizing thermal performance are introduced.