A Time Predictable Heterogeneous Multicore Processor for Hard Real-time GALS Programs
Conference: ARCS 2016 - 29th International Conference on Architecture of Computing Systems
04/04/2016 - 04/07/2016 at Nürnberg, Deutschland
Proceedings: ARCS 2016
Pages: 8Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Salcic, Zoran; Nadeem, Muhammad; Striebing, Bjoern (Department of Electrical and Computer Engineering, University of Auckland, Auckland, New Zealand)
Time-predictability of the execution architecture is a key requirement for successful implementation of hard real-time systems. This paper presents a scalable and fully time-predictable multicore processor, TP-HMP, that comprises of two types of time-predictable cores and a novel NoC interconnect that are used in creation of heterogeneous multiprocessor FPGA SoCs. The NoC interconnect, called TDMA-MIN, is based on a combination of time-division multiple access and multistage interconnect resulting in very good throughput and bounded latency. TP-HMP is used as the execution platform for hard real-time programs written in the GALS language SystemJ. The platform allows application of static timing analysis to SystemJ programs and can be used in design space exploration targeting multiple cores. As such, TP-HMP is the first real-time capable multicore processor supporting execution of SystemJ GALS programs.