Synchronization of MPI One-Sided Communication on a Non-Cache-Coherent Many-Core System
Conference: ARCS 2016 - 29th International Conference on Architecture of Computing Systems
04/04/2016 - 04/07/2016 at Nürnberg, Deutschland
Proceedings: ARCS 2016
Pages: 6Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Christgau, Steffen; Schnor, Bettina (Institute for Computer Science, University of Potsdam, August-Bebel-Str. 89, 14482 Potsdam, Germany)
This paper discusses the design and implementation of MPI’s general active target synchronization on the Intel Single-Chip Cloud Computer, a non-cache-coherent many-core CPU. Measurements show a performance benefit of a factor of four compared to the default SCC-tuned MPI implementation and demonstrate the feasibility of implementing efficiently a shared memory protocol despite the lack of cache coherence. Further, a classification of implementation designs of MPI’s general active target synchronization is presented.