Analysis of Packaging Impedance on Performance of SiC MOSFETs

Abstract:
This paper presents an analysis of the impact of packaging impedances for high-performance SiC MOSFET's, building on previous packaging analysis performed by the author [1] and others (e.g., [2]-[3]). Devices from the same fabrication lot were assembled into two standard discrete package types (TO-247 and TO-263), and subjected to a range of frequency-domain and time-domain analysis procedures. The objective of this work is to provide an understanding of the performance limitations imposed by standard package types, and to evaluate whether the TO-263 package provides a measurable advantage over the larger TO-247 package in the context of high-edge-rate-capable SiC MOSFET's. Frequency-domain analysis was utilized to extract parasitic impedance estimates for each of these two package types; and the TO-263 package is shown to have 32% lower inductance in the drain-source path compared to the TO-247 package. In addition, empirical switching experiments were carried out with identical conditions for devices in these two packages, and a comparison is presented on the basis of switching dynamics and switching energy calculated from time-domain waveforms. Empirical results reported here indicate that the total per-cycle switching losses are reduced by 29% in the TO-263 package as compared to the TO-247 package at a load current of 20 A, all other conditions being equal. This difference is found to be attributable to a small reduction in the common source inductance of the TO-263 package compared to the TO-247 package.