Ultra Low-Power Array Processor 1-D Test Structure Implementation
Conference: CNNA 2016 - 15th International Workshop on Cellular Nanoscale Networks and their Applications
08/23/2016 - 08/25/2016 at Dresden, Deutschland
Proceedings: CNNA 2016
Pages: 2Language: englishTyp: PDFPersonal VDE Members are entitled to a 10% discount on this title
Paasio, Ari (Technology Research Center, University of Turku, Turku, Finland)
Array processors, and vision chips in particular, have mostly been designed from maximum processing speed point of view. There are applications in e.g. surveillance field, where the image content is analyzed rather rarely and where on the other hand the power consumption is of greater importance due to battery operation functionality. In sensing applications it is customary to use a coarser sensing for triggering a finer tuned sensor, where the coarse sensor is optimized for lower power and where the sensing abilities have been relaxed to that of a triggering ability. In this paper we continue on reporting on the progress of PMOS only based 1-D propagation network research, where the target of the structure is to achieve extremely low power consumption even at the cost of somewhat increased silicon area. A layout test structure has been designed and sent to fabrication. The layout area required by the PMOS only structure is reported for the first time.